A semiconductor device such as an IC (integrated circuit) generally has electronic circuit elements such as transistors, diodes and resistors fabricated integrally on a single body of semiconductor material. The various circuit elements are connected through conductive connectors to form a complete circuit which can contain millions of individual circuit elements. Advances in semiconductor materials and processing techniques have resulted in reducing the overall size of the IC while increasing the number of circuit elements. Additional miniaturization is highly desirable for improved IC performance and cost reduction. Interconnects provide the electrical connections between the various electronic elements of an IC and they form the connections between these elements and the device's external contact elements, such as pins, for connecting the IC to other circuits. Typically, interconnect lines form the horizontal connections between the electronic circuit elements while conductive via plugs form the vertical connections between the electronic circuit elements, resulting in layered connections.
A variety of techniques are employed to create interconnect lines and vias. One such technique involves a process generally referred to as dual damascene, which includes forming a trench and an underlying via hole. The trench and the via hole are simultaneous filled with a conductor material, for example a metal, thus simultaneously forming an interconnect line and an underlying via plug. Examples of conventional dual damascene fabrication techniques are disclosed in Kaanta et al., "Dual Damascene: A ULSI Wiring Technology", Jun. 11-12, 1991, VMIC Conference, IEEE, pages 144-152 and in U.S. Pat. No. 5,635,423 to Huang et al., 1997.
The prior art techniques, such as those disclosed in the above referenced publications, rely on forming the trench and the via hole for the dual damascene structure in the same etching step shown in FIGS. 1A-1D. As depicted in FIG. 1A, a first dielectric layer 110 is deposited on a semiconductor substrate 112. An etch stop layer 116, such as silicon nitride, is deposited on first dielectric layer 110. A second dielectric layer 118 is deposited on etch stop 116, and an etch mask 120 is positioned on dielectric layer 118. Etch mask 120 is patterned (121) for etching a via hole, having a width W1. Second dielectric layer 118 is etched using a first anisotropic etch procedure to form a hole 122 (FIG. 1A) conforming to the via pattern. This etching procedure is stopped at etch stop layer 116. Etch mask 120 is removed and another etch mask 124 (see, FIG. 1B) is positioned on second dielectric layer 118 such that it is patterned (126) for forming a trench which is intended to include the previously formed hole 122 conforming to the via pattern. However, when the trench pattern is misaligned with hole 122 (see, FIG. 1B), portion 123 of hole 122 is covered by mask 124. As shown in phantom, a second anisotropic etch procedure is used to etch the trench pattern through second dielectric layer 118. Simultaneously, hole 122 is extended to substrate 112, by etching through etch stop layer 116 and through first dielectric layer 110. In this dual damascene technique the first etch procedure has a greater selectivity to etch stop layer 116 than the second etch procedure.
As shown in FIG. 1C, the second etch procedure results in forming trench 128 and via hole 130 which extends to semiconductor substrate 112. It will be noted that portion 123 of trench 128 is a widened portion of the trench due to the misalignment between via pattern 121 and trench pattern 126. However the widened portion 123 is not contiguous with underlying via hole 130, thereby reducing via pattern width W1 (FIG. 1A) to via hole width W2 (FIG. 1C). In other words, the width of the via hole is smaller than the width of the via pattern as a result of the misalignment. This prior art technique has other shortcomings as well, e.g. undeveloped resist (not shown) remaining on the bottom of hole 122, thereby impeding the complete etching of hole 130, and attack on the etch stop during via etch. Also, this procedure requires an etch chemistry which is very selective with respect to photoresist materials, which is difficult to achieve with dielectrics such as those having a low dielectric constant.
Mask 124 is removed, after which trench 128 and via hole 130 are simultaneously filled with a suitable conductive metal 132 (see, FIG. 1D) forming metallized line 134 and via plug 136 which contacts substrate 112. Excess metal 132 is removed from the surface of layer 118, for example by planarizing, to define line 134. Dual damascene line 134 has a widened section 138 resulting from the via misalignment, but this widened section is not contiguous with via plug 136, thus resulting in a reduced plug width as compared with the width of the via pattern.
Prior art techniques for forming via holes and trenches suitable for dual damascene fabrication result in a reduced via width when the trench pattern and the via pattern are misaligned, as described above in connection with FIGS. 1A-1D, particularly when the trench pattern width is substantially the same as the via pattern width. A significant reduction in via width makes it more difficult to fill the via hole with conductive metal, particularly when the via hole has a relatively high aspect ratio. Filling difficulties can result in filling the via incompletely, causing electrical or mechanical failure of the dual damascene structure. Also, a reduced width of the via results in a reduced contact area between the interconnect line and the underlying via plug, which can cause a highly disadvantageous increase in the contact resistance between the line and the via plug. Also, the prior art techniques described in connection with FIGS. 1A-1D result in widening the line at the misalignment point. Widening a line can result in an electrical short between closely spaced adjacent lines.
Accordingly, the need exists for improved methods for dual damascene fabrication to compensate for misalignment between the via mask and the trench mask and to overcome fabrication problems resulting from the presence of undeveloped resist impeding the complete formation of via holes as well as the need for etch chemistry which is very selective with respect to photoresist and etch stop layers.